This invention relates generally to digital-to-analog conversion circuitry and more particularly to digital-to-analog conversion circuitry adapted for monolithic integrated circuit fabrication.
As is known in the art, digital-to-analog converters (DAC's) have a wide range of applications. One type of monolithic integrated circuit DAC includes an R-2R resistor ladder network. With such ladder network, a current is produced in a first rung of the network and the current through each succeeding rung is reduced by a 2:1 factor. Thus, the ladder network generates in the rungs thereof binarily weighted currents. The binarily weighted current produced through each rung of the ladder network is coupled to a switch. Each switch is activated, or deactivated, selectively in response to a corresponding bit of the digital word being converted to couple, or decouple, the current to, or from, an output bus selectively in accordance with the logical state of the bit. The binarily weighted currents are thus selectively coupled to the output bus and are thereby combined to produce a resultant current through the output bus proportional to the digital word being converted. As the resolution requirements for the DAC are increased, the number of bits of the digital word being converted are correspondingly increased and the accuracy of the current produced in the first rung of the R- 2R resistor ladder network becomes correspondingly more critical. For example, in a 12 bit DAC using the R-2R resistor ladder network described, the accuracy of the resistor in the first rung thereof must be held to an accuracy of within 0.02 percent of its ideal value.
One technique suggested for reducing the high degree of accuracy required for the first resistor of the R-2R ladder network has been to provide 2.sup.N identical current sources, where N is the number of bits in the digital word being converted. Because of the relatively large number of current sources required, however, as where a 12 bit DAC is desired, a compromise has been suggested where the R-2R ladder network is used for conversion of the least significant bits of the digital word, (for example, the 9 least bit significant bits of a 12 bit digital word) while the use of eight identical current sources is used in the conversion of the three most significant bits of the digital word. The currents coupled to an output bus from the eight identical current sources selectively in accordance with the three most significant bits are added with the currents produced in the rungs of the R-2R ladder network and selectively coupled to the output bus in accordance with the 9 least significant bits of the digital word so that, based on the principle of superposition, the total current flow produced through the output bus is proportional to the entire 12 bits of the digital word. With such arrangement, an error in the level of the current produced by any one of the eight "identical" current sources reduces the accuracy of the DAC. Therefore, to fully realize the advantage of such technique, the switching circuitry used to couple a selected one, or ones, of the eight current sources to the output bus should not contribute significantly to errors in the levels of currents produced by such current sources.
One switching circuit which has been suggested, however, does contribute errors in producing the desired output current. One source of error in such switching circuit arises from the fact that since any practical current source generally has a finite output impedance, the actual current supplied by the current source is related to the voltage applied to its output terminal. With the switching circuit suggested, the voltage applied to the output terminal of any one of the current sources is a function of the logical states of the bits of the digital word being converted and hence the amount of current produced by such current source is not independent of the digital word being converted. Further, an additional source of error with such switching circuitry in producing the proper current flow through the output bus arises from the fact that the current supplied by each current source passes to the output bus through a plurality of different electrical paths dependent on the digital word being converted. Each electrical path includes an active npn transistor and hence, since the transistors in the different electrical paths have different alphas (collector current to emitter current gain ratios) and since the bits of the digital word are fed to the base electrodes of such transistors and the current produced by the current source flows to the output bus through the emitter-collector electrodes of the transistor in its path, the amount of current actually contributed by such current source to the total flow of current through the output bus is dependent on the digital word being converted. Still further, the switching circuit suggested produces switching signals for the base electrodes of the transistors which differ in level variation depending on the digital word being converted so that when larger variations in signal level are produced, the switching times of the transistors responding to such signals are increased.